SADR capacitors

What is a SAR DAC?

DAC: The DAC is the main component of the SAR ADC. The advantage of the capacitive DAC is that it has no DC power consumption, the capac-itors can be integrated in CMOS processes with a good accuracy. The binary weighted structure allows up to 10 bits accuracy, for 10 MHz and 10 fJ/conversion step.

How much power does a SAR ADC consume?

The filter and the ADC together consume 39.2μW for an output rate of 10 MS/s. This paper presents a compact 10-b successive approximation register analog-to-digital converter (SAR ADC) in 65-nm CMOS with an integrated passive finite impulse response (FIR) filter for anti-aliasing.

Which capacitive DAC architecture is best for 10-bit SAR ADCs?

Abstract: This paper presents a detailed comparison between the two commonly used capacitive DAC architectures for 10-bit SAR ADCs: binary-weighted and split-capacitor DACs. These DAC architectures are compared based on the impact of unit-capacitor mismatch and parasitic capacitance on their linearity, area and power consumption.

Does a window capacitor calibration scheme improve linearity of a 16-bit SAR ADC?

Abstract: A 16-bit 1-MS/s SAR ADC was fabricated in 180nm digital CMOS. To maintain excellent linearity, a window capacitor calibration (WCC) scheme is proposed to estimate capacitor mismatch and obtain corrected bit weights.

What is a 10B SAR ADC?

The 10-b SAR ADC occupies only 36 × 36 μm, thanks to the small-size DAC, and by placing the ADC circuits directly under the capacitors. The ADC was tested at 10 and 30 MS/s and achieves an effective number of bits of 9.18/9.10 bit with an figure-of-merit of 4.1/4.4 fJ per conversion-step, respectively.

How are capacitors fabricated?

The capacitors are fabricated leveraging the conformal atomic layer deposition of a metal-insulating-metal nanocoating, using TiN and either Al 2 O 3 or HfAlO x with 20 and 40 nm, into ultra-high aspect-ratio (up to 100) trenches etched in silicon with size of 2 μm and pitch of 4 μm (density of 62500 trenches/mm 2 ).